SPI CPOL and CPHA choose which clock edge data is sampled on: mismatch means garbage

SPI has four clock modes defined by two bits: CPOL (clock polarity: idle high or idle low) and CPHA (clock phase: sample on first or second edge). A device is only guaranteed to correctly receive data in the mode it was designed for. If master and peripheral are in different modes, the data appears shifted or garbled with no error signal: SPI has no acknowledgement mechanism. The device datasheet always specifies which mode (0, 1, 2 or 3) to use.

/* STM32 HAL SPI mode constants */
/* Mode 0: CPOL=0 CPHA=0: most common for sensors */
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase   = SPI_PHASE_1EDGE;

/* Mode 1: CPOL=0 CPHA=1 */
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase   = SPI_PHASE_2EDGE;

/* Mode 3: CPOL=1 CPHA=1: used by many SD cards and some ADCs */
hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
hspi1.Init.CLKPhase   = SPI_PHASE_2EDGE;